Advances in non-volatile memory technology include resistance-based memory technologies, such as Magnetoresistive Random Access Memory (MRAM). MRAM technology is an emerging non-volatile memory technology that employs ferromagnetic-based Magnetic Tunnel Junctions (MTJs) as the basic memory elements. A commonly used array architecture for MRAMs is the one-transistor, one-MTJ (1T1MTJ) architecture. As the name suggests, each bit cell in this architecture consists of an MTJ connected in series with an n-channel metal-oxide-semiconductor (NMOS) access transistor. In order to leverage the increased density and area reduction advantages associated with scaling down NMOS technologies, it is desirable to use smaller transistors and lower operating voltages for the MRAM bit cell. However, while scaling down NMOS technology into the deep submicron regime yields area and density benefits, difficulties may arise in designing an 1T1MTJ architecture with stable operation, particularly with respect to a source loading effect.